Boundary Scan (BSCAN) is a standardized method of board testing of the Joint Test Access Group (JAG), a consortium founded in 1988 comprising over 200 companies from the semiconductor, testing and system integration fields, and in 1990 the method was formally approved as industry standard IEEE I'D for Test Access Port (TAP) and Boundary Scan (BSCAN) architectures. All connection tests at board level in the production of complex Printed Circuit Boards (PCBs) are based on this specification. If the object under test has its own microprocessor as well as flash-based program memory, a built-In self-test can for example be implemented by loading a flash memory via Boundary Scan with the aid of a self-test program. Test results stored in the memory can again be read out using Boundary Scan once the test has ended.
IEEE 1149.1 is today increasingly replacing In-Circuit Test (ICT) methods since the complexity of the integrated semiconductor circuits (ASICs and FPGAs) to be tested is increasing and as a result the possibility of accessing these components for test purposes, by providing additional test pads on the test object, is becoming ever more difficult. Thus, over the last decades, an exponential increase of the number of connection pins with diameters becoming increasingly smaller has been seen. This trend was accelerated even further by the introduction of the Ball Gate Array (BGA) technology, which brought with it the relocation of the connecting pins to the underside of the module. The solution lay in integrating conventional tests on microchips, such as interruption or short circuit tests, into the chips themselves and planning in a path referred to as the “boundary” for scanning the digital information. Flexible platforms in accordance with the Peripheral Component Interconnect (PCI) or PCI Extensions for Instrumentation (PXI) Standard currently allows the detection of BSCAN controllers and BSCAN software as well as its integration into the relevant PCI or PXI platform. This enables complex solutions to be developed combing conventional function tests and BSCAN-based tests into one universal test platform.
To execute Boundary Scan tests two conditions must be met: At least a few of the integrated circuits (ICs) on the board must comply with the Boundary Scan specification. During testing a BSCAN register is then made to perform the desired test with the aid of test vectors. In addition the product developer must make available a scan path between the individual ICs which leads from a Test Access Port (TAP) through the ICs back again to the TAP where the data is finally scanned. For testing of electrical connections Boundary Scan tests represent an excellent alternative to In-Circuit Tests (ICTs). The costs for performing the function testing are low, and because of the increasing integration and miniaturization of terminals, it can be assumed that there will be a continuing trend towards Boundary Scan.
Whereas the Boundary Scan method according to IEEE 1149.1 has previously primarily been used as an innovative technology for function checking of integrated circuits or for verification and simulation of hardware malfunctions, recent developments have shown that there are further possible applications for this principle. As well as its use for test purposes, Boundary Scan is also very effectively deployed for in-system-programming of flash memories and also Programmable Logic Device (PLD) chips, for example Field Programmable Gate Arrays (FPGAs) with up to 10,000 logic gates per array, or Programmable Logic Arrays (PLAs). In this case the individual control and address inputs of a flash memory are stimulated via the chained BSCAN cells of a BSCAN register assigned to these inputs such that a read or write operation is optionally initiated. As can be seen from the basic functional diagram shown in FIG. 1, the data here can be output or recorded by the corresponding BSCAN cells.
FIG. 3 shows information about the steps required which have to be initiated via the TAP Controller for a write or programming operation. In a first step the address, data and a Module Select (CS) signal are output. Then the WRITE signal is activated in a second step, with nothing changing in the other signals. Finally, in a third step the WRITE signal is deactivated without changing the other signals.
The problem is that programming is made very time-consuming by this method since three cycles of the entire BSCAN register are required for one write operation.
Conventional methods in accordance with the prior art resolve this problem either by shortening the BSCAN chain or by direct control of the WRITE input:                a) Since the programming time depends on the length of the BSCAN chain, the programming can be accelerated in the first case by reducing the chain by the BSCAN cell necessary for flash programming and activating with a separate instruction (SHORTEX) instead of the usual instruction (EXTEST).        b) In the last case the flash memory can be stimulated directly with the aid of an additional signal which is output via the TAP Controller defined in the IEEE 1149.1 Standard. This requires the test or programming equipment to support the control of an additional signal and an additional pin to be provided on the module for this interface embodied as a plug-in connection.        